The present invention relates generally to computer bus architectures and to system-on-a-chip architectures with multi-port processors, including but not limited to embedded processors, application specific integrated circuits (ASICS), Field Programmable Arrays (FPGAs) and other programmable devices.
System-on-a-chip (SoC) design allows a designer to create complex silicon systems from smaller working blocks or systems. By providing a method for easily supporting proprietary functionality in a larger context that in a larger context that includes many existing design pieces, SoC design facilitates the use of silicon design for many systems. There are three views of traffic for a design which are important to differentiate, a memory centric view, a processor centric view and an input/output (I/O) view. Traditionally, prior art systems tend to be processor centric and not balanced. It is desirable that an SoC does not compromise one view over another and provides equal optimization. If all three traffic aspects of an SoC are fully scaleable, the applications for this SoC can be unlimited.
The typical SoC design includes a central processing unit (CPU), memory and peripherals communicating over a fast bus (for the CPU and memory) and a slow bus (for the peripherals). Because the CPU, memory, and peripherals (when accessing memory) share the same bus, bus latency can be problematic. When using a single port processor, the processor must compete with the rest of the SoC system for the bus and memory resources. This latency can be even more problematic in hierarchical bus systems. For example a first peripheral can send data to a second peripheral by writing the data to memory, which is then read by the second peripheral. During the time data is being written or read, neither the CPU nor other peripherals can access the memory or the bus providing access to the memory. A bus arbiter can be employed to control access to the bus. However, the bus arbiter adds to the overhead in accessing the bus and can cause even more latency.
One solution to the aforementioned problems is to use larger caches. Another solution is to increase the clock speed (frequency) of the bus system. Yet another solution is to provide dedicated memory interfaces for the critical design parts of the SoC. However, these approaches are expensive. Furthermore, these approaches can introduce other problems, e.g. increasing the clock speed (frequency) of the system bus requires more power and generates additional heat.
There are three views of SoC traffic that should be differentiated, that is the memory centric view, the processor centric view, and the input/output (I/O) view. Preferably, a SoC doesn't compromise one view over another and provides equal optimization. The application for a SoC with equal optimization can be unlimited if all three traffic aspects are fully scaleable.
Thus it is desirable to minimize latency for accessing memory, while operating the memory bus at the lowest possible clock speed and yet provide a high data transfer rate.